quicnios

generated 2009.12.03.16:33:30

Overview

  clk  quicnios
   epcs_flash_controller
 dclk  
 sce  
 sdo  
 data0  
   leds
 out_port  
 rxd  
 txd  
Processor
   cpu_0 Nios II 9.0
Peripherals
   cpu_0 altera_nios2 9.0
   tri_state_bridge altera_avalon_tri_state_bridge 9.0
   epcs_flash_controller altera_avalon_epcs_flash_controller 9.0
   vector altera_avalon_onchip_memory2 9.0
   sysid altera_avalon_sysid 9.0
   leds altera_avalon_pio 9.0
   timer altera_avalon_timer 9.0
   jtag_uart altera_avalon_jtag_uart 9.0
   uart altera_avalon_uart 9.0
cpu_0
 instruction_master  data_master
  cpu_0
jtag_debug_module  0x00000800 0x00000800
  epcs_flash_controller
epcs_control_port  0x00001000 0x00001000
  vector
s1  0x00004000 0x00004000
  sysid
control_slave  0x00000000
  leds
s1  0x00000020
  timer
s1  0x00000040
  jtag_uart
avalon_jtag_slave  0x00000008
  uart
s1  0x00000060

clk

clock_source v9.0


Parameters

clockFrequency 20000000
clockFrequencyKnown true
  

Software Assignments

(none)

cpu_0

altera_nios2 v9.0
clk clk   cpu_0
  clk
instruction_master   tri_state_bridge
  avalon_slave
data_master  
  avalon_slave
instruction_master   epcs_flash_controller
  epcs_control_port
data_master  
  epcs_control_port
d_irq  
  irq
instruction_master   vector
  s1
data_master  
  s1
data_master   sysid
  control_slave
data_master   leds
  s1
data_master   timer
  s1
d_irq  
  irq
data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
data_master   uart
  s1
d_irq  
  irq


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSetsPresent false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_numShadowRegisterSets 1
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_eicPresent false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_autoAssignNumShadowRegisterSets true
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave epcs_flash_controller.epcs_control_port
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Tiny
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave vector.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 20000000
breakSlave cpu_0.jtag_debug_module
breakOffset 32
  

Software Assignments

CPU_IMPLEMENTATION "tiny"
CPU_FREQ 20000000u
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x4020
RESET_ADDR 0x1000
BREAK_ADDR 0x820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_MULTIPLY_PRESENT 0
HARDWARE_MULX_PRESENT 0
HARDWARE_DIVIDE_PRESENT 0
INST_ADDR_WIDTH 20
DATA_ADDR_WIDTH 20

tri_state_bridge

altera_avalon_tri_state_bridge v9.0
clk clk   tri_state_bridge
  clk
cpu_0 instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   cy7c1049cv33
  avalon_tristate_slave_0


Parameters

registerIncomingSignals true
  

Software Assignments

(none)

cy7c1049cv33

cy7c1049cv33 v1.0.1
tri_state_bridge tristate_master   cy7c1049cv33
  avalon_tristate_slave_0


Parameters

sharedPorts
  

Software Assignments

(none)

epcs_flash_controller

altera_avalon_epcs_flash_controller v9.0
clk clk   epcs_flash_controller
  clk
cpu_0 instruction_master  
  epcs_control_port
data_master  
  epcs_control_port
d_irq  
  irq


Parameters

autoSelectASMIAtom true
useASMIAtom false
  

Software Assignments

REGISTER_OFFSET 1024

vector

altera_avalon_onchip_memory2 v9.0
clk clk   vector
  clk1
cpu_0 instruction_master  
  s1
data_master  
  s1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName vector
instanceID NONE
memorySize 16384
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "vector"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 16384u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

sysid

altera_avalon_sysid v9.0
clk clk   sysid
  clk
cpu_0 data_master  
  control_slave


Parameters

id 1632405225
timestamp 1259879606
  

Software Assignments

ID 1632405225u
TIMESTAMP 1259879606u

leds

altera_avalon_pio v9.0
clk clk   leds
  clk
cpu_0 data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg true
captureEdge false
clockRate 20000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 3
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 1
DATA_WIDTH 3
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

timer

altera_avalon_timer v9.0
clk clk   timer
  clk
cpu_0 data_master  
  s1
d_irq  
  irq


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 20000000
timeoutPulseOutput false
timerPreset CUSTOM
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 20000000u
LOAD_VALUE 19999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

jtag_uart

altera_avalon_jtag_uart v9.0
clk clk   jtag_uart
  clk
cpu_0 data_master  
  avalon_jtag_slave
d_irq  
  irq


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
writeBufferDepth 64
writeIRQThreshold 8
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

uart

altera_avalon_uart v9.0
clk clk   uart
  clk
cpu_0 data_master  
  s1
d_irq  
  irq


Parameters

baud 9600
baudError 0.02
clockRate 20000000
dataBits 8
fixedBaud true
parity NONE
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts false
useEopRegister false
  

Software Assignments

BAUD 9600
DATA_BITS 8
FIXED_BAUD 1
PARITY 'N'
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 0
USE_EOP_REGISTER 0
SIM_TRUE_BAUD 0
SIM_CHAR_STREAM ""
FREQ 20000000u

generation took 0.02 seconds
rendering took 4.55 seconds